The present invention relates to the manufacture of integrated circuits. More particularly, the present invention provides a technique for forming a gettering layer in a silicon-on-insulator wafer made using a controlled cleaving process, for example.
Integrated circuits are fabricated on chips of semiconductor material. These integrated circuits often contain thousands, or even millions, of transistors and other devices. In particular, it is desirable to put as many transistors as possible within a given area of semiconductor because more transistors typically provide greater functionality, and a smaller chip means more chips per wafer and lower costs.
Some integrated circuits are fabricated on a slice or wafer, of single-crystal (monocrystalline) silicon, commonly termed a xe2x80x9cbulkxe2x80x9d silicon wafer. Devices on such xe2x80x9cbulkxe2x80x9d silicon wafer typically are isolated from each other. A variety of techniques have been proposed or used to isolate these devices from each other on the bulk silicon wafer, such as a local oxidation of silicon (xe2x80x9cLOCOSxe2x80x9d) process and others. These techniques, however, are not free from limitations. For example, conventional isolation techniques consume a considerable amount of valuable wafer surface area on the chip, and often generate a non-planar surface as an artifact of the isolation process. Either or both of these considerations generally limit the degree of integration achievable in a given chip.
An approach to achieving very-large scale integration (VLSI) or ultra-large scale integration (ULSI) is by using a semiconductor-on-insulator (SOI) wafer. An SOI wafer typically has a layer of silicon on top of a layer of an insulator material. A variety of techniques have been proposed or used for fabricating the SOI wafer. These techniques include, among others, growing a thin layer of silicon on a sapphire substrate, bonding a layer of silicon to an insulating substrate, and forming an insulating layer beneath a silicon layer in a bulk silicon wafer. In an SOI integrated circuit, essentially complete device isolation is often achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. An advantage SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
SOI offers other advantages over bulk silicon technologies as well. For example, SOI offers a simpler fabrication sequence compared to a bulk silicon wafer. Devices fabricated on an SOI wafer may also have better radiation resistance, less photo-induced current, and less cross-talk than devices fabricated on bulk silicon wafers. However, many problems that have already been solved regarding fabricating devices on bulk silicon wafers remain to be solved for fabricating devices on SOI wafers.
Numerous limitations, however, still exist with the fabrication of SOI wafers. For example, devices within integrated circuits in SOI wafers are very sensitive to the presence of even minute concentrations of some impurities. For example, metals, such as copper, nickel, silver, gold, or iron, within the active region of a device typically degrade several device characteristics, including leakage current and breakdown voltage. These and other metals rapidly diffuse through silicon at temperatures typical of semiconductor device fabrication processes. These impurities often become trapped in the active region of the SOI wafer. That is, the SOI wafer includes a dielectric layer or insulating layer underlying the active region that tends to keep impurities in the active layer, rather than diffusing down into the bulk silicon. Accordingly, SOI wafers are prone to device and reliability problems caused by the presence of impurities that cannot diffuse out of the active region.
From the above, it is seen that a technique for removing impurities from active regions of an integrated circuit made on an SOI wafer is highly desirable.
According to the present invention, a technique including a method and device for removing impurities from an SOI wafer made using a controlled cleaving process is provided. In an exemplary embodiment, the present invention provides an SOI wafer with a gettering layer for removing impurities from an active region. This gettering layer removes impurities from the device, thereby preventing a possibility of quality and reliability problems, e.g., lowered breakdown voltage, increased leakage current, and the like. Additionally, the gettering layer provides for xe2x80x9clifetimexe2x80x9d engineering of the device made on the SOI wafer.
In a specific embodiment, the present invention provides an SOI wafer made by way of a xe2x80x9ccleavingxe2x80x9d process with an implanted gettering layer. The process includes a step of providing an SOI wafer, where the thin layer of material (e.g., silicon) was bonded onto an insulating layer. Gas-forming particles, such as hydrogen or helium ions, are implanted or introduced into the thin layer of material or other region of the SOI wafer. The SOl wafer is thermally processed so that the implanted particles create, for example, microbubbles or implanted precipitates in the wafer. These microbubbles act as gettering sites for impurities in the thin layer of material. Alternatively, the particles act as gettering sites for the impurities. The thin layer of material has been separated from, for example, a bulk donor silicon wafer by a controlled cleaving process, such as the one described in U.S. Provisional Application Serial No. 60/046,276 in the name of Henley et al. (xe2x80x9cHenleyxe2x80x9d), which is hereby incorporated by reference for all purposes.
In an alternative embodiment, the present invention provides an SOI wafer made by way of a cleaving process with a deposited gettering layer. The gettering layer is, for example, a layer of polysilicon, which can be patterned, formed on a bulk monocrystalline silicon donor or receptor wafer. The thin layer of material, including the gettering layer, has been separated from, for example, a bulk donor silicon wafer by a controlled cleaving process. A gettering layer, such as a layer of polysilicon, on the thin layer, such as a layer of monocrystalline silicon, can provide effective gettering after a different time-temperature product, i.e. thermal budget, than microbubbles. Thus, a gettering layer on the thin layer can be used in addition to or alternatively to microbubble or particle gettering sites.
Numerous benefits are achieved by way of the present invention over pre-existing techniques. These benefits include, among others, gettering of impurities from active regions of an integrated circuit device made on an SOI wafer. Additionally, the present invention occurs by way of improved processing techniques using PIII, for example. PIII is relatively cost effective, easy to use and in some instances produces less impurity metal contamination than other ion implantation techniques. Furthermore, the present technique provides xe2x80x9clifetimexe2x80x9d engineering of the device, which is likely to have improved reliability from the present gettering layer(s). These and other benefits are described throughout the specification and more particularly below.
These and other embodiments of the present invention, as well as its advantages and features are described in more detail in conjunction with the text below and attached figures.